Contest Information

Background

Even though there is widespread emphasis on platform design which takes advantage of block re-use in order to reduce development cost and time to market, almost every successful leading-edge product introduced requires one or more novel, high performance block(s) in order to capture market share. For example, new multiprocessor chips need ever faster I/O circuitry in order to get their data into and out of off-chip memory and take advantage of all the processing power available. New wireless products, while using many already proven blocks, require higher performance from components such as faster, wider bandwidth LNAs and ADCs to meet the new flexibility requirements for software-controlled radios. Mixed-signal circuits as well as processors need faster PLLs with greater tuning ranges. Communications circuits need faster clock and data recovery circuits with lower bit error rates. SoCs need very fast and accurate thermal sensing and control circuits to prevent damage during operation. Handheld devices require fast, high resolution graphics engines with low power. All circuits require high performance ESD circuitry that can operate effectively without otherwise degrading the intended function. High performance can apply not only to circuit speed, but also to other specifications that improve operation and enable a new product to have a significant market advantage: power, bit error rate, accuracy, bandwidth, operating voltage, gain, linearity, efficiency, etc. New high performance products are often the result of circuit innovations.

Contest Objectives

The key objective of the SRC/SIA IC Design Challenge is for university teams to create novel, high performance circuit designs that make end products more competitive. These products can be digital, analog, mixed-signal or wireless. Using the provided technology and design kit, successful contest teams will design circuits that clearly demonstrate potential for high performance for a target application offering advantages over existing designs. Specific circuitries of particular interest to the sponsors are LNAs, mixers, high speed I/Os, low power, high resolution graphics and thermal management; however the contest is not limited to these areas. Sponsors are looking for creativity, innovation, and the best usage of the given technology to implement an important new or improved circuit or circuit subsystem. A secondary objective is to assist faculty in stimulating greater interest in IC design careers among students, both graduate and undergraduate and from diverse populations.

Participant Eligibility

This SRC/SIA High Performance Design Challenge is open to North American university teams composed of faculty and students.. Multiple teams may enter the contest from each university. Teams may consist of graduate and undergraduate students and must have a faculty team leader; an assistant faculty team leader is optional. Teams are encouraged to have one or more undergraduates from diverse populations participate on the team with objective of creating interest in careers in microelectronics. Industry personnel may participate as consultants to the teams on a limited basis with approval from contest leaders.

Contest Structure

The contest will consist of two phases: Phase One, a design phase, and Phase Two, a fabrication and evaluation phase. Contest entries in the form of a brief white paper outlining the proposed design must be submitted via the online SRC GRC submission process no later than September 4, 2007 3P.M. ET. SRC will screen these submissions and announce the field of Phase One teams by September 15, 2007. They must then complete their design and render a comprehensive design report by February 20, 2008 for judging. In addition to the monetary awards to the winners of Phase One, the five top entries as selected by the contest judges will then be eligible to participate in Phase Two where they will complete physical designs of their circuits and submit their layouts for fabrication on Jazz Semiconductor's 180nm SiGe process (SBC18 P/H). Winners will be selected and prizes awarded after each of these phases.

Awards

The top three Phase One entries will win cash prizes for their university departments of $10,000, $5,000, and $3,000 for first, second, and third places. These Phase One awards will be presented in June 2008. Five of the Phase One teams will be invited to prove their designs in the Jazz 180nm SiGe process. Fabricated chips will be packaged for evaluation by Quick Pak. The value of this Phase Two award is approximately $100K per team (includes library/design kits, mask and wafer fab, packaging and support). Judges will select three top winners from Phase Two to be awarded cash prizes of $25,000, $15,000, and $10,000 for first, second and third places. All cash awards will be provided as gifts to the winning universities in the name of the faculty team leader to be used in support of IC design education programs at the university and to provide a monetary award to the winning student(s). The final awards will be presented in February 2009. Cash prizes may be subject to change. In addition, other non-cash prizes may be awarded as appropriate.

Criteria

• Creativity
  • Novel circuit architectures or circuit subsystems exploiting unique high performance opportunities
  • Creative combinations of cores in development of a useful application demonstrating high performance aspects
• Impact
  • Anticipated impact of the design on future application spaces
  • Performance gains relative to similar functions implemented in prior designs and documentation of these improvements
  • Reliability assessments of the circuit (e.g., electromigration, thermal considerations, etc.), including steps taken to show how such reliability concerns were considered during the design
• Efficiency
  • Efficient reuse of proven cells and cores
  • Minimize die area: primary consideration will be given to die sizes less than 2.4mm x 2.4mm; absolute max die size will be 5mm x 5mm.
  • Demonstrated substantial power-performance gains using radical new architecture and circuit concepts
• Test
  • In Phase One - Provisions for the efficient test of the circuit
  • In Phase Two - Test procedures utilized, the degree to which test data correlates with Phase One performance predictions, and recommendations for improvements in extractions and modeling tools for the given technology
• Completeness
  • Complete submission in accordance with contest submission guidelines
• Design Practice
  • Sound design techniques and thoroughness must be demonstrated and documentation provided for each phase of the design. In Phase Two, designs must function and clearly demonstrate intended high performance aspects.
• Broader Impact
  • Teams that demonstrate how they have involved a diverse cadre of undergraduate students will benefit (i.e. have one or more undergraduates on the team or give a presentation to an undergraduate class about their project, etc.)

Intellectual Property

The university or universities from which the designs originate will own all rights to submitted designs.

Library/Design Kit

A cell library including I/Os as well as design kits with cell layouts, LVS, DRC files, etc., can be made available under agreement with Jazz Semiconductor by September 15, 2007. An authorized representative of the University will be required to sign an appropriate Non-Disclosure Agreement (NDA), which must be strictly followed. The design kits will be available throughout the contest and afterwards under the terms of the agreement as long as the team leader maintains control, and provided advanced notice and clearance of any new users to Jazz. Further details on how to download the design kits will be forthcoming. Teams are encouraged to use their own previously developed cells and cores and to use open source cores found at various university and other web sites (including www.opencores.org). Teams are responsible for ensuring/verifying the integrity of any cells/cores that they use in their design. SRC will establish a contest forum on the SRC website at the start of the contest for participating teams to exchange technical discussions and post any questions to contest administrators. Teams are encouraged to make good use of this forum and to extend help each other.

Submission Requirements (dates subject to change)

• September 4, 2007 - All papers must be submitted by 3 P.M. ET. Contest entries will consist of a 2-4 page white paper, including any drawings, description of the design to be undertaken. Lead faculty and team contact information, identifying main point of contact, must be included. The entry must clearly indicate how the design will excel in one or more areas of high performance and, if possible, exploit the technology used. The entry should also include past IC design experience.
• September 15, 2007 - List of Phase One participating teams will be posted to the SRC website. See www.src.org/ICcontest/default.asp for a list of teams and other announcements.
• October 1, 2007 - Resumes for all participating students must be submitted to SRC for posting to the SRC website to validate contest entry. Instructions for submitting resumes will be provided by e-mail when Phase One teams are notified.
• February 20, 2008 - A technical report including a Preliminary Design Review must be submitted to SRC explaining the purpose of the circuit designed, the design methodology used, the high performance aspects, simulated performance data results, preliminary layout (floor plan) of the design, and how the design was verified. This report must also include a plan to verify the final layout in Phase Two and a plan to evaluate and test the final fabricated design. This report and the above judging criteria will be the basis for selecting winners of Phase One and participants for Phase Two.
• March 15, 2008 - The Phase One Winners will be announced and the Phase One Top Five teams will be invited to participate in Phase Two.
• June 9, 2008 - Presentation of Phase One awards. Winners (top three) of Phase One (one student and one faculty representative per winning team) will be invited to attend DAC, with reasonable expenses paid, and possibly present their designs via posters.
• May 15, 2008 - Phase Two Initial Submissions from Phase One Top Five teams. Final design, layout, and test review documents must be submitted to SRC. GDSII layout files that are 180nm Jazz SBC18 technology compatible for the physical design of the circuit must be submitted to Jazz for fabrication as prescribed by Jazz. Layout data must pass all LVS and DRC requirements and meet any pre-defined checklist provided by Jazz.
• September 25, 2008 - Fabricated devices will be returned to the universities for packaging, testing and analysis.
• November 20, 2008 - Phase Two Final Submissions. A final report on actual silicon evaluation must be submitted to SRC, including a description of test methodology, resulting data, and comparison with performance estimates from Phase One. In case of design or layout errors, winning designs must, as a minimum, demonstrate major functionality and aspects of intended high performance in order to be awarded full prize amounts.
• February 9, 2009 - Presentation of final awards. Winners of Phase Two (one student and one faculty representative per winning design) will be invited, reasonable expenses paid, to present their designs via posters and receive grand prize awards at the International Solid State circuits Conference.