Participating Organizations



  • 3D Glass Solutions, Inc.
  • AMD
  • Amazon
  • Analog Devices
  • Ansys
  • Applied Materials
  • Arizona State University
  • ASM
  • Binghamton University
  • Boeing
  • Broadcom
  • Cadence
  • Cardea Bio
  • Cepheid
  • Cirrus Logic
  • Cisco Systems Inc.
  • Clarkson University
  • DARPA
  • Duke University
  • GA Tech
  • GlobalFoundries
  • Google
  • Hewlett Packard Enterprise
  • Howard University
  • IBM
  • IMEC
  • IIT/Kanpur - India
  • Innovation Impact Partners
  • Intel
  • Iowa State University
  • IPC
  • Kepler Computing
  • Khalifa University - UAE
  • Mass. Institute of Technology
  • Materials Research Society
  • MediaTek
  • Memcus
  • Micron
  • Mitre
  • Morgan State University
  • Mubadala Technology
  • NIST
  • Nokia
  • NCSU
  • Northrop Grumman
  • NXP
  • Oregon State
  • ORNL
  • PNNL
  • Penn State
  • Purdue University
  • Qualcomm
  • Raytheon
  • Rigaku
  • Rochester Inst. Tech.
  • Samsung
  • Sandia National Lab
  • SEMI
  • Siemens EDA
  • Silicon Intervention Inc.
  • SK hynix Inc.
  • Skywater Technologies
  • Softmems
  • Stanford University
  • SUNY Poly
  • Synopsys, Inc.
  • Texas Instruments
  • Tokyo Electron Ltd.
  • Tower Semiconductor
  • TSMC
  • Twist Bioscience
  • Uhnder
  • UC/Irvine
  • UC/San Diego
  • UC/Santa Barbara
  • Univ. Florida
  • UIUC
  • Univ. Michigan
  • Univ. Notre Dame
  • UT/Dallas
  • University of Toronto
  • Washington State University
  • Western Digital
  • Zero Asic

NIST Microelectronic and Advanced Packaging Technologies (MAPT) Roadmap

Advanced Packaging, along with 3D monolithic and heterogeneous integration, will be the key enabler of the next microelectronic revolution. In fact, advanced packaging+3D is becoming the equivalent of transistor of the 2D Moore’s Law era. This initiative closely aligns with SRC’s Decadal Plan, which stresses the urgency of increased research funding in this area.  

MAPT Roadmap Technical Working Groups

  • TWG A: Workforce Development
  • TWG B: Application Drivers & System Requirements
  • TWG C: Advanced Packaging & Heterogeneous Integration
  • TWG D: Digital Processing
  • TWG E: AMS Processing
  • TWG F: Photonics & MEMS

Objective

The main objective of this initiative is to accelerate United States’ leadership in semiconductors, where the industry-relevant opportunities lie at the confluence of Microelectronic and Advanced Packaging Technologies, or MAPT. SRC and its partners will accomplish this by: (1) forming a consortium that includes stakeholders from all parts of the supply chain, (2) identifying emerging applications that will drive future microelectronics and packaging needs, and (3) developing a roadmap that guides technology development, manufacturing advances, and workforce development. The roadmap will support continued efforts by the consortium and other groups as a guide for the broader R&D community and future Manufacturing USA Institutes in microelectronics and advanced packaging.

MAPT is a critical multidisciplinary field with the potential to transform the design and manufacture of future microchips. These advances build upon breakthroughs in advanced packaging, 3D monolithic and 2.5D/3D heterogeneous integration, electronic design automation, nanoscale manufacturing, and energy-efficient computing. The Semiconductor Research Corporation’s 2030 Decadal Plan for Semiconductors identified five seismic shifts to attack through innovative MAPT research and development.

Read the press release or the Request for Information submitted to Commerce: Incentives, Infrastructure, and Research and Development Needs to Support a Strong Domestic Semiconductor Industry.

Victor Zhirnov, Chief Scientist

zhirnovVictor Zhirnov is Chief Scientist at the Semiconductor Research Corporation. He is responsible for envisioning new long-term research directions in semiconductor information and communication technologies for industry and academia. Victor serves as the Chair for the 2030 Decadal Plan for Semiconductors and as the Director for the MAPT Roadmap.

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