2024 Innovation Award
US 9687877B2: "Compute Memory"
Issued in 2016, this influential research was produced by the project “Stochastic Information Processing Systems” (2385.001), which was part of the Systems On Nanoscale Information fabriCs (SONIC) Center. One of the authors, Naresh Shanbhag, was the Director of the SONIC Center, which was part of the SRC/DARPA STARnet program.
https://patents.google.com/patent/US9697877B2/
https://www.src.org/library/patent/p1515/
This patent presents compute memory, a technique which utilizes a multi-row read configuration and embedded analog signal processing to perform computations including addition, subtraction, absolute, multiplication, inner product, division, and their combinations. Compute memory can achieve energy efficiency due to low-voltage swing operation both in the memory read and computation processes. In addition, since the compute memory bit-cell array structure can be identical to that of a standard memory array, the storage density, and the read/write functionality of the standard memory array are preserved without incurring delay and energy penalties. Compute memory can further reduce delay through its intrinsically parallel column-wise operation, thereby overcoming a limited IO bus width between memory and computation logics. The research in this patent resulted in a major technology transfer to DARPA by enabling the establishment of the OPTIMA program, a research effort focused on developing ultra-energy-efficient AI chips.