Session 13 - Logic and Physical Design Tools (TECHCON 2016)

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Monday 12-Sep-2016 3:40 - 4:55 PM San Antonio
Session 13 - Logic and Physical Design Tools
13.1 3:40 PM GRC
Finite Difference Time Domain Analysis of Stress Evolution and Void Growth for General Interconnect Wires

Chase W. Cook (UC/Riverside)
13.2 3:55 PM GRC
Slew-Driven Clock Tree Synthesis (SLECTS) Methodology to Facilitate Low Voltage Clocking

Weicheng Liu (Stony Brook)
13.3 4:10 PM GRC
Concurrent Guiding Template Assignment and Redundant via Insertion for DSA-MP Hybrid Lithography

Jiaojiao Ou (UT/Austin)
13.4 4:25 PM GRC
Control Synthesis and Delay Sensor Deployment for Efficient ASV Designs

Chaofan Li (Texas A&M)
13.5 4:40 PM GRC
Exploring Submodularity for Circuit Uncertainty Quantification

Chong Li (Univ. of Washington, Intel Fnd/SRCEA Fellow)

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