Session 2 - Integrated System Design I (TECHCON 2016)

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Monday 12-Sep-2016 9:00 - 10:15 AM San Marcos
Session 2 - Integrated System Design I
2.1 9:00 AM STARnet
Power Efficient, Hierarchical, Introspection Framework for HPC Systems

Yeseong Kim (UC/San Diego)
2.2 9:15 AM STARnet
RAPID: Accelerating Pattern Search Applications with Reconfigurable Hardware

Kevin Angstadt (Univ. of Virginia)
2.3 9:30 AM STARnet
MR.NITRO: Distributed Accelerators for MapReduce on CMPs

Abraham Addisie (Univ. of Michigan)
2.4 9:45 AM GRC
Autoscaling of Cores in Multicore Processors Using Power and Thermal Workload Signatures

Rupesh R. Karn (Masdar Inst.)
2.5 10:00 AM GRC
Configurable Logic vs. A Sea of Dark Silicon Accelerators

Tian Tan (UT/Austin)

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