• Tuesday 13-Sep-2016 10:30 - 11:45 AM San Antonio
  • Session 21 - Test II
  • 21.1 10:30 AM GRC
  • Assessing the Impact of RTN on Logic Timing Failures Using a 32nm Dual Ring Oscillator Array Based Test Structure
    Qianying Tang (Univ. of Minnesota)
  • 21.2 10:45 AM GRC
  • BIST-RM: BIST-Assisted Reliability Management of SoCs Using On-Chip Clock Sweeping and Machine Learning
    Mehdi Z. Sadi (Univ. of Florida)
  • 21.3 11:00 AM GRC
  • Efficiency Analysis for Test-Point Insertion in LBIST
    Miao He (Univ. of Florida)
  • 21.4 11:15 AM GRC
  • Retention Testing Methodology for STTRAM
    Anirudh S. Iyengar (Univ. of South Florida)
  • 21.5 11:30 AM GRC
  • Achieving Perfect Multi-Defect Diagnosis in Regular Circuits
    Benjamin Niewenhuis (Carnegie Mellon Univ., IBM/SRCEA Fellow)

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