• Monday 12-Sep-2016 9:00 - 10:15 AM Pecos
  • Session 4 - Memories
  • 4.1 9:00 AM STARnet
  • A Unified Framework for Error Correction in On-Chip Memories
    Henry Duwe (UIUC)
  • 4.2 9:15 AM STARnet
  • Memory-Consistency-Model-Aware ISA Design and Specification
    Caroline J. Trippel (Princeton)
  • 4.3 9:30 AM STARnet
  • Improving the Efficiency of Spintronic Memories through Approximate Storage
    Ashish Ranjan (Purdue)
  • 4.4 9:45 AM NRI
  • Spintronic Memory Benchmarking Based on a Novel Three-Transistor Nonvolatile SRAM Cell
    Chenyun Pan (Georgia Tech)
  • 4.5 10:00 AM NRI
  • Write Error Rate of Spin-transfer-torque Random Access Memory Including Micromagnetic Effects using Rare Event Enhancement
    Tanmoy Pramanik (UT/Austin)

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