Secure, Trustworthy, Assured and Resilient Semiconductors and Systems (STARSS) Workshop

  • Date:
    Wednesday, May 21, 2014, 6 p.m. — Thursday, May 22, 2014, 5 p.m. PT
    Location:
    Fairmont Hotel, Gold Room, 170 Market Street, San Jose, CA, United States
    Event ID:
    E005440
E005440 image

This invitation only T3S workshop will convene experts from industry, academia and government to assess the threats, capabilities and gaps related to secure, trustworthy, assured and resilient semiconductors and systems, and to identify research to improve these characteristics without unduly impacting cost or performance.

Organizing Committee

  • Ron Perez, AMD
  • Claire Vishnik, Intel
  • Chris Daverse, SRC (Consultant)
  • Celia Merzbacher, SRC