SRC Heterogeneous Integration Colloquium

  • Date:
    Tuesday, Sept. 11, 2018, noon–5 p.m. PT
    Stanford University, Paul Allen Building,CISX 101, 330 Serra Mall, Stanford, CA, United States
    Event ID:

Heterogeneous Integration in Packaging

The ability to package advanced products with increased functionality into smaller form factors and volumes with higher performance, lower power and lower cost presents attractive differentiation for product manufacturers.  While many heterogeneous integration solutions are very application specific with short lead times, it is the focus of this colloquium to identify the highest value, pre-competitive university research on heterogeneous integration to the semiconductor industry.  The following topics will be discussed during the colloquium with respect to the highest value, pre-competitive university research1:

  • Applications:  Mobile, IoT, medical, automotive, high performance computing, defense

  • Components:  Single chip and multi chip packaging, photonics, power electronics, sensors, RF and mixed signal 

  • Design:  System design and simulation tools 

  • Integration Processes:  SiP, 3D, 2.5D, WLP 

  • Cross Cutting Topics:  Enabling materials, emerging research devices, interconnects, test, supply chain and security  

1  Similar topics are discussed in the IEEE Heterogeneous Integration Roadmap from an industry centric perspective.

Attendance at the colloquium is by invitation only.  For more information contact

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