Proposers' Day Workshop for the Joint University Microelectronics Program 2.0 (JUMP 2.0)

1. Proposers who intend to display a poster at the workshop should send a copy in pdf format to JUMP-2.0-solicitation@src.org no later than January 18 at 3:00 pm ET. The words “POSTER: [Include the Author’s first and last name/university]” must appear in the subject line of the email. The email must also contain the names and university affiliations of all researchers who will be associated with the research, as well as the theme name with which the poster is associated. Theme names are noted below. Please also refer to the needs document. If this deadline is not met by the presenter, the SRC does not guarantee a space for display of your poster at the event.
2. Posters that meet the guidelines above will be displayed on 30 x 40 easel space within Gather Town. 
3. The title of the research, the proposed JUMP 2.0 theme*, the principal investigator’s name(s), and the university affiliation(s) should be clearly shown on your poster. *Individual task whitepapers are encouraged to provide both the primary JUMP 2.0 theme and an alternate JUMP 2.0 theme.
4. SRC will assign you a poster number within Gather Town
5. During the poster session, we ask that you stay close to your poster to discuss your research with sponsors in attendance.
6. NOTE: Please consider that the poster session is virtual when putting your poster together. Some reviewers (sponsors) will be looking at your poster without the opportunity to speak with you due to time differences so ensure your research idea/message will be clearly understood.

Seven Systems (S) & Technology (T) Themes

1. Cognition (S): Next-generation AI systems and architectures
2. Communications and Connectivity (S): Efficient communication technologies for ICT systems.
3. Intelligent Sensing to Action (S): Sensing capabilities and embedded intelligence to enable fast and efficient generation of actions
4. Systems and Architectures for Distributed Compute (S): Distributed computing systems and architectures in an energy efficient compute and accelerator fabric
5. Intelligent Memory and Storage (S): Emerging memory devices and storage arrays for intelligent memory systems
6. Advanced Monolithic and Heterogeneous Integration (T): Novel electric and photonic interconnect fabrics and advanced packaging .
7. High-performance Energy-Efficient Devices for Digital and Analog Applications (T): Novel materials, devices, and interconnect technologies to enable next-generation digital and analog applications