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SRC/SIA Webinar: Collaboration Towards Decadal Plan Goals: Emerging Semiconductor Technologies

Date:

Thursday, Sept. 29, 2022, 12:30 p.m.–2 p.m. ET

Location:

Webinar, Washington, DC, United States

Event ID:

E007686

Purpose

The SRC-NIST nCORE (nanoelectronic COmputing REsearch) program sets and aggressive research agenda for Emerging Semiconductor Technologies. Examples include advanced spintronic materials and devices, defect-engineered ferroelectrics for emerging memory devices, exploring new materials and physics concepts based on a first principles, revolutionary thermal management solutions, innovative metrology, etc. Research vectors include novel computing paradigms, fundamental material, device, and interconnect research, advanced manufacturing and nanofabrication, innovative metrology and characterization, and computational models.

The main goal of the webinar is to present the “success stories” from SRC’s nCORE program with NSF, NIST, and industry partners, and identify a compelling research agenda for the next wave of semiconductor manufacturing based on the Decadal Plan for Semiconductors.

Presenters

Opening Remarks

Eric Breckenfield is the director of technology policy at the Semiconductor Industry Association (SIA), where he directs SIA’s research and development activities as well as the association’s education and workforce development efforts. Prior to joining SIA, Eric was a Lead Scientist at Booz Allen Hamilton where he served as a consultant for predominantly U.S. defense clients, including DARPA and the U.S. Naval Sea Systems Command in the areas of electronic materials and device physics, robotics and autonomy, and hardware/supply chain security. Before joining Booz Allen Hamilton, Eric was an AAAS Science and Technology Policy Fellow with the White House’s National Nanotechnology Initiative where he led the Sustainable Nanomanufacturing and Nanoelectronics for 2020 and Beyond initiatives. Previously, Eric was a National Research Council Fellow at the Naval Research Laboratory.

Presenter

Stacey Bent is the Jagdeep and Roshni Singh Professor at Stanford University, where she is Professor of Chemical Engineering and Professor, by courtesy, of Chemistry, of Materials Science and Engineering, and of Electrical Engineering. She also currently serves as Vice Provost for Graduate Education and Postdoctoral Affairs. Bent obtained her B.S. degree in chemical engineering from UC Berkeley and her Ph.D. degree in chemistry from Stanford, and she was a postdoctoral fellow at AT&T Bell Laboratories. Bent’s research interests are in the understanding of surface chemistry and materials synthesis and the application of this knowledge to a variety of problems in sustainable energy, semiconductor processing, and nanotechnology. Her group’s research on atomic layer deposition (ALD) ranges from fundamental mechanistic studies, to area selective ALD, to applications in solar cells, fuel cells, catalysts, and batteries. Bent has published over 300 peer-reviewed papers, holds 6 patents, and has presented over 330 invited talks. She has supervised 50 Ph.D. students and 25 postdoctoral scholars. Bent was elected to the U.S. National Academy of Engineering in 2020. She is also a Fellow of the American Chemical Society (ACS) and the American Vacuum Society (AVS). She is the recipient of the 2018 ACS Award in Surface Chemistry, the 2020 SRC Technical Excellence Award, and the 2021 ALD Innovator Award, the highest recognition in the ALD community. In 2021, she also was honored with the Braskem Award for Excellence in Materials Engineering and Science from the American Institute of Chemical Engineers (AIChE).

Panelists

	Joerg Appenzeller Dr. J. Appenzeller received the M.S. and Ph.D. degrees in physics from the Technical University of Aachen, Germany in 1991 and 1995. His Ph.D. dissertation investigated quantum transport phenomena in low dimensional systems based on III/V heterostructures. He worked for one year as a Research Scientist in the Research Center in Juelich, Germany before he became an Assistant Professor with the Technical University of Aachen in 1996. During his professorship he explored mesoscopic electron transport in different materials including carbon nanotubes and superconductor-semiconductor-hybride devices. From 1998 to 1999, he was with the Massachusetts Institute of Technology, Cambridge, as a Visiting Scientist, exploring the ultimate scaling limits of silicon MOSFET devices. From 2001 until 2007, he had been with the IBM T.J. Watson Research Center, Yorktown, NY, as a Research Staff Member mainly involved in the investigation of the potential of carbon nanotubes and silicon nanowires for a future nanoelectronics. Since 2007 he is Professor of Electrical and Computer Engineering at Purdue University and Scientific Director of Nanoelectronics in the Birck Nanotechnology Center. In 2014 he became the Barry M. and Patricia L. Epstein Professor of Electrical and Computer Engineering. His current interests include novel high performance and energy efficient electronic devices based on low-dimensional nano-materials as nanowires, nanotubes, graphene and di-chalcogenides as well as spintronics devices for beyond von Neumann computing architectures, including probabilistic computing.
	Blanka Magyari-Köpe is currently a Technical Manager in R&D, TCAD Division at TSMC in San Jose, CA since early 2019. She received her Ph.D. degree in Physics in 2003 from the Royal Institute of Technology in Sweden, did postdoctoral studies at UCLA, and went on to continue her research at Stanford University as Senior Research Engineer. Her scientific interest has been in interdisciplinary research, focused on developing atomistic models to tackle nanoscale phenomena that includes characterization of defects, manipulating interfaces at atomic level, improving thin film depositions and material optimizations for advanced semiconductor devices. She is Senior IEEE Member since 2017 and her awards include the 2018 Dennis Gábor prize for innovation in memory technology from Novofer Foundation. During her career Dr. Magyari-Köpe has been on the committees of IEDM Modeling and Simulation and Memory Technology, SISPAD and ESSDERC, co-organized sessions at APS and ECS, co-edited the book “Advances in non-volatile memory and storage technology” published by Elsevier, served as Associate Editor for Journal of Computational Electronics and organized a special Focus Topic Issue on “Computational Electronics of Emerging Memory Elements”. She has given over 40 invited talks, and co-authored 100 scientific papers and 4 patents.
	Jian-Ping Wang is the Robert F. Hartmann Chair and a Distinguished McKnight University Professor of Electrical and Computer Engineering, and a member of the graduate faculty in Physics and Chemical Engineering and Materials Science at the University of Minnesota. He received the information storage industry consortium (INSIC) technical award in 2006 for his pioneering work in exchange coupled composite magnetic media, which enabled doubling the areal density for the perpendicular magnetic recording. He is a recipient of the outstanding professor award for his contribution to undergraduate teaching in 2010. He is also the recipient of 2019 SRC Technical Excellence Award for his innovations and discoveries in nanomagnetics and novel materials that accelerated the production of magnetic random-access memories. He is the director of the Center for Spintronic Materials for Advanced Information Technology (SMART), one of three SRC/NIST nCORE research centers. He is a fellow of IEEE, APS and National Academy of Inventors.
	Judy Cha is a Professor at Cornell University in the Department of Materials Science and Engineering. Her group has pioneered in synthesis and transport studies of topological nanomaterials. Funded by the SRC nCORE IMPACT program, her group recently demonstrated low resistivity of topological metal nanowires attractive for interconnect applications. She is a recipient of the SRC Young Faculty Award (2021), Moore Foundation EPiQS Materials Synthesis Investigator Award (2019), NSF CAREER (2018), and IBM Faculty Award (2014). She received her Ph.D. from Cornell University in 2009 and did post-doctoral research at Stanford University. Prior to joining the faculty at Cornell in 2022, she was a faculty member at Yale University in the Department of Mechanical Engineering and Materials Science for 9 years.
	David Gundlach is Chief of the Nanoscale Device Characterization Division of the Physical Measurement Laboratory (PML) at the National Institute of Standards and Technology (NIST). The Division transforms nano- and atom-scale technologies by advancing measurement science and fundamental knowledge. Dr. Gundlach received his B.S. in Physics in 1992, and M.S. and Ph.D. in Electrical Engineering in 1997 and 2001, respectively, from The Pennsylvania State University. After graduate school, Dr. Gundlach joined IBM’s Zürich Research Laboratory as a postdoctoral researcher and in 2003 joined Eidgenössische Technische Hochschule (ETH) Zürich as a research staff member in the Department of Solid-State Physics. In 2005, Dr. Gundlach joined the National Institute of Standards and Technology in Gaithersburg, MD, as the leader of the Thin Film Electronics Project in the Semiconductor Electronics Division. From 2016 to 2017, he was on detail as a program analyst to the Office of the Under Secretary for Standards & Technology, and NIST Director. He is a member of the IEEE and APS, and a former editorial board member for IEEE Transactions on Electron Devices.

Roundtable Moderator

Steve Kramer serves as University Research Manager for Micron in the Technology Development Group, helping to mentor, identify and vet new semiconductor memory-related science. Steve started his career at Micron doing chemical mechanical planarization (CMP) where he helped standardize in-situ and ex-situ measurement techniques for enhancing process control. He followed one of his side-projects, related to supercritical fluid deposition, into technology pathfinding and university project liaison work. This knack for technology dabbling has also led him to garner more than 50 patents and to publish a research paper from time to time. He is currently active in helping define the memory technology roadmap with various external collaborators. Initially earning a degree in Chemistry from the College of Idaho, Steve subsequently achieved an advanced degree in Materials Science and Engineering from the University of California, Los Angeles, researching chemical routes to ceramics and flexible aerogels. Steve has also had the chance to serve as a visiting researcher at Nippon Sheet Glass, Japan, studying non-wettable, sol gel-derived coatings, and as a Research Scholar at Stanford University, investigating the potential of magnetic tunnel junctions for memory applications.