Call for Research in High Performance Digital Circuit Design

Introduction

The SRC announces a call for new research in High Performance Digital Circuit Design. Details of submission requirements and schedule appear later in this announcement.

Topics of interest include but are not limited to the following:

  • Novel circuit topologies for implementing logic functions which:
    • Comprehend, leverage, and manage the effects of large subthreshold source-drain leakage currents and large gate leakage currents
    • Rethink signal to noise ratios from the device level up to the circuit level, for signal swings in the range of microvolts to millivolts
    • Address statistical variability issues (see below)
    • Minimize noise generation which interferes with sensitive analog and RF functions on the same substrate
  • Design techniques which deal with statistical variability induced by (for instance):
    • Small numbers of dopant atoms
    • Patterning near the diffraction limits of light
    • Die-to-die and across-die variations comparable to gate lengths
  • Digital circuits which exploit new device structures and novel process technologies
  • Novel device structures which implement complex logic functions at the device level, especially for memory functions
  • Alternative and novel approaches to logic power reduction
  • Low voltage power electronics for innovative DC-DC conversion in sub-100 nm technologies
  • Circuit Techniques that comprehend upgradeability, including reconfiguration and fault tolerance
  • Memory architectures with integrated per-bit processing
  • New approaches to synchronous systems that reduce requirements on clock skew, jitter, and power delivery

Special Requirements

  • The SRC sponsors an ongoing program to develop predictive SPICE models for sub-100 nm technologies, and will make appropriate models available to researchers. Proposals for circuit techniques that are not applicable beyond the 100 nm node of the ITRS will not be accepted.
  • Research which seeks to develop advanced logic families must address related issues of testability, scalability, and system-level performance, including power, noise, and manufacturability
  • Researchers are strongly encouraged to include plans for fabrication and evaluation of their designs, using MOSIS or SRC member company foundries.
  • The total annual budget for all projects funded under this Call is approximately $700,000. Individual projects will typically involve one or two faculty and one or two students. The budget for any single project may not exceed $200,000 annually for three years.

Submission Process

Submissions will be in two phases. In phase one, interested parties are invited to submit one-page white papers. A subset of the white papers received will be selected, and their authors invited to submit full proposals. A subset of the full proposals will be selected for funding. Details of this process, and examples of the required white paper contents and format, are given here.

Schedule

The solicitation and evaluation process will be conducted on a very compressed schedule. Please note the short times for submission of white papers and full proposals:

Date Milestone
December 11, 2000 This solicitation published
January 12, 2001 Deadline for one-page white paper submission
February 2, 2001
  • Notification of selection or non-selection of white papers.
  • Invitation of full proposals from selected white papers.
February 23, 2001 Deadline for full proposal submission
April 4, 2001 Notification of acceptance or non-acceptance of proposals
May 1, 2001 Start of funding for accepted proposals.

For more information, contact Justin Harlow at (919) 941-9400.

4819 Emperor Blvd, Suite 300 Durham, NC 27703 Voice: (919) 941-9400 Fax: (919) 941-9450