Request for White Papers: Semiconductor Device Compact Modeling for Circuit Design

Semiconductor Research Corporation is seeking white papers from the international university community for research directed to development of compact models of integrated semiconductor devices suitable for use in circuit design1. The intent of this research is to aid SRC's member companies in their efforts to efficiently and accurately design digital, RF and analog integrated circuits using next generation single-gate bulk and multiple-gate non-classical semiconductor devices. Compact models resulting from this research should be capable of reproducing the device terminal behavior with accuracy, computational efficiency, ease of parameter extraction, and relative model simplicity for simulating a circuit or a system using current and future CMOS technology nodes. This solicitation specifically addresses modeling device electrical characteristics related to digital (models for ultra thin oxide effects, leakage current, etc.) and mixed signal applications (models for noise, cross-talk effects, etc). ). The computational efficiency of any new model is important and should be addressed during model development, and effort should be made to improve computational efficiency where possible.

The research solicited is focused on three areas. The first and most important area is development of the Next Generation Compact Model. This model should incorporate all physics relevant to future technology generations with a small number of model parameters compared to models used in industry today. It should be fully symmetric, model all intrinsic capacitances and, as such, be capable of using a small number of extraction parameters to model analog and RF performance of MOSFETs representing the most advanced technology nodes. Further, it is highly desirable that this model can be used for the extrapolation of future technologies and device parameter variation based on technology fluctuations. The second area for research is to support the industry's need for continued development of the industry-standard, public domain models [BSIM (Berkeley Short-channel Insulated gate Model)] currently used to design single-gate CMOS, partially-depleted SOI, and fully-depleted SOI integrated circuits. New developments for these existing models include improved accuracy through inclusion of new transistor electrical effects observed in future CMOS technologies and through improved mathematical behavior of the model equations. The third area for research, of equal priority to the second area, is to develop a new compact model(s) for the new non-classical CMOS devices. These devices include ultra-thin body FD-SOI, channel engineered devices (e.g., strained Si, SiGe, SiGeC, and non-silicon-based channels), and the variety of multiple-gate CMOS devices. This model should accurately include quantum mechanical carrier dynamics through the self-consistent solution of the Poisson and Schroedinger equations or through an equivalent methodology. Although compact models in this category will be pioneers in a new field, the industry's expectations of accuracy and computational efficiency must be achieved in this model.

Additional information regarding technology barriers and prioritized research needs associated with this solicitation will be found in the documents "Research Needs for Semiconductor Device Compact Modeling" and "SRC-NSF Mixed-Signal Workshop May 16-17, 2002". Following a review by SRC member companies, some of the white papers will be selected as finalists and these authors will be invited to submit full detailed proposals for research. Selection of the programs to fund will be made from these proposals.

1 "Compact Modeling" of semiconductor devices refers to the development of models for integrated devices for use in circuit simulations by designers. In contrast "Device Modeling", which is not included in this solicitation, is concerned with the understanding and nature of detailed physical representations of semiconductor devices and is usually done as TCAD (Technology Computer Aided Design) in support of device and process design.

White Paper, Proposal and Program Timetable
Event Deadline
Publication of Request for White Papers April 29, 2003
White Papers Due to SRC May 23, 2003
Invitation to Submit Proposals June 13, 2003
Proposals Due to SRC July 18, 2003
Preliminary Notification of Decision of Review Team August 22, 2003
Notification of Final Program Selection Results September 16, 2003
Program / Funding Starts October 1, 2003

 

 

 

 

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