Grant Application for: Cross-disciplinary Semiconductor Research (CSR)


SRC-GRC is soliciting grant applications in Cross-disciplinary Semiconductor Research.

The goal of this initiative is to foster exploratory, multi-disciplinary, high-risk university research leading to novel high-payoff solutions for the science and technology challenges faced by the semiconductor industry at and beyond the time horizons of the International Technology Roadmap for Semiconductors (ITRS). Successful CSR projects will offer innovative and, hopefully, disruptive solutions to the challenge of enabling exponential gains in cost/performance benefits provided by the semiconductor industry for the foreseeable future, and may lead to novel applications for this industry and may enhance the population of non-traditional researchers/out of box thinkers working with the SRC.

The role of this program is to stimulate non-traditional thinking about the issues facing the semiconductor industry. It is intended to seed new research and programs for the SRC-GRC and SRC-FCRP. Consistent with the incubator role of the initiative, these will be 1 year non-overhead bearing grants at a funding level of $40K. Awardees are encouraged to develop a proposal for follow-on funding of expanded programs by the SRC-GRC, SRC-FCRP or other agencies. Follow-on funding will depend on the availability of funds and strategic plan alignment.


The scope of this solicitation is Nanoscale CMOS-Based Architectures. The challenge: Sustaining CMOS value progression through functional scaling and system design

Although in one to two decades, the industry will approach the limits to the physical scaling of CMOS devices, we postulate that exponential increases in functionality per unit cost can be sustained and perhaps even accelerated through functional scaling and system design. We seek proposals to address this challenge as follows:

  1. Heterogeneous, multicore, embedded (on chip) processor technology, including system and software research
  2. Application driven research for interfacing this processor to the many functional units such as sensors, communications, data storage, etc.

The integration level for nanoscale electronic devices could eventually be in the range of 1010 - 1011 devices/cm2. At this level, long interconnects represent a challenge to operation (energy consumption), design and manufacturing (irregular arrays of interconnects with arbitrary connections). Also, nanoscale CMOS (and other nanoelectronic elements), are likely to suffer from significantly higher failure rates than their contemporary counterparts. In addition, low energy operation requirements and small transistor dimensions are likely to result in higher thermal and quantum error rates. Given these realities, future nanoscale technology may map more naturally into novel information processing and computing architectures. Also, a wide range of new ideas have been proposed for beyond CMOS technology scaling, such as molecular electronics, carbon nanotube devices, spin devices etc. Most likely, these options will unfold their full potential only in combination with new and appropriate nanoarchitectures that integrate alternative electronic devices on to a silicon platform. A possible ultimate evolution of on-chip architectures is heterogeneous multi-core organized with hierarchical processors. Such an architecture might consist of a central general-purpose CMOS core and a relatively large number of application-specific processors and systems either in CMOS or otherwise implementing a specific macro-function. Or, alternatively, the architecture might be a distributed decision-making system, where the 'supervision' function is provided by different processors, depending on the application.

Proposals are sought that:

  • Provide a framework for the design of the computational models for heterogeneous multi-core on-chip architectures, perhaps with hierarchical structure
  • Develop prototype applications for heterogeneous/hierarchical information processing systems
  • Offer gains in functionality and performance as result of integrating non-CMOS devices (e.g. sensors) and emerging nanoelectronic devices into CMOS platform

Grant Application Guidelines

Responses are limited to 3 pages, using at least a 10-point font, and MUST BE SUBMITTED VIA THE SRC WEB SITE by TUESDAY, MAY 1, 3 PM EDT/12 PM PDT. Non-compliance with these guidelines may exclude your grant application from consideration.

Please include the following identifying information on your grant application:

  • Project title
  • Investigator(s)
  • University
  • Telephone number, mailing address and e-mail address

Please address the following in your grant application:

  • Approximately 100 word executive summary
  • Problem to be addressed: explain the rationale for the project in terms of the semiconductor industry needs
  • Objective: what do you plan to do?
  • Novelty: the basic concept and discuss the role of cross-disciplinary research in providing a unique solution to the problem addressed
  • Approach: strategy for addressing the problem
  • Research output: identify possible research products of a successful research program
  • IP: identify pre-existing intellectual property, if any

Timetable and Deadlines

Event Deadline
Deadline to Submit Grant Applications Tuesday, May 1, 2007, 3 PM EDT/12 PM PDT
Notification of Final Program Selection Results August 1, 2007
Program/Funding Start September 1, 2007

Please direct all technical questions to Dr. Victor Zhirnov, (, 919-941-9454).
All other questions should be directed to Leslie Faiers, (, 919-941-9455).

4819 Emperor Blvd, Suite 300 Durham, NC 27703 Voice: (919) 941-9400 Fax: (919) 941-9450

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