Call for Research in Modeling & Simulation of Nanoelectronic Materials, Processes, and Devices


The Semiconductor Research Corporation (SRC) Global Research Collaboration (GRC) in Device Sciences is soliciting white papers in the area of modeling and simulation (M&S) of nanoelectronic materials, processes, and devices. The principal goals of this discovery-driven program are to apply M&S techniques to understand and overcome fundamental scientific barriers to extending Digital CMOS and related technologies to their ultimate limits, to the development of novel memory technologies, and to the development of high performance analog and mixed-signal technologies. These goals will be accomplished by linking the proposed theoretical modeling and simulation program with on-going experimental studies of nanoelectronic materials and devices.

This call for white papers, issued to universities worldwide, may be addressed by an individual investigator or by a research team. A successful white paper submission is expected to result in an invitation to submit a full proposal, in a competitive procurement, leading to a 3-year research contract. The number and size of the contracts awarded will be determined by the amount of available funds and by the number of high quality proposals received. The funding amount or anticipated level of effort is expected to be in the range of $50,000 to $200,000 per year. The intentionally broad funding range is meant to allow a bidder flexibility to propose sufficient effort and resources to accomplish the objectives of this solicitation. Proposals offering substantial funding leverage are strongly encouraged.

Research Needs

Specific, prioritized Modeling and Simulation Research Needs are summarized in a research needs document recently prepared by Device Sciences' Modeling and Simulation Thrust. Needs in the Compact Modeling area are addressed by a separate Device Sciences Thrust and are not included in this solicitation.

The largest groups of research needs identified are in the area of Digital CMOS. Although these are divided into Evolutionary and Revolutionary categories, and between process modeling and device modeling areas, we strongly encourage comprehensive research that bridges across areas to deliver fundamental understanding of the relationships between processing conditions and device performance, including coupling to experimental work. We also encourage research across the modeling hierarchy from very detailed physical descriptions to approaches more directly applicable for industrial technology analysis.

In the process modeling area the Research Needs prioritization is clearly weighted towards Evolutionary CMOS topics reflecting our assessment that the state-of-the-art here continues to lag behind current industry needs. Even so, the focus of white papers should be targeting the 16-nm node and beyond, consistent with the overall strategy for the Device Sciences area. Process modeling for beyond-silicon technologies is also of high interest. Device modeling priorities include 3D modeling of device properties and variability for silicon-based devices, and three related topics in beyond-silicon devices encompassing physical modeling of device transport, the role of contacts, and efficient simulation of transport including scattering.

The research needs summary also calls out two additional areas of research focus beyond Digital CMOS, corresponding to two other thrust areas within Device Sciences. White papers in the Memory area are solicited applying M&S to address fundamental challenges in non-classical memory applications such as MRAM, phase change memory, and nanocrystal-based memory. In Analog and Mixed-Signal technologies, white papers are solicited addressing fundamental challenges in areas such as emerging materials and passives, and in high performance I/O.

White Paper Guidelines

White Papers are limited to 2 pages (at least 10 pt. font) and must be submitted via the SRC Web site. Non-compliance with these guidelines will exclude White Papers from consideration. White Papers must be submitted via the SRC GRC Web site by Monday, JUNE 16, 2008, 3 PM EST/12 PM PST. White papers not meeting these requirements will not be considered.

Please include the following identifying information in your white paper:

  • Project title
  • Investigators
  • University
  • Principal Author telephone number, mailing address, and e-mail address

Please address the following topics in your white paper:

(Note that the inclusion of general background on the semiconductor industry challenges and general references to Moore's Law may not be the best use of your space).

  • Background: emphasize area and problem to be addressed; describe why research is being done; rationalize value in terms of semiconductor industry needs.
  • Approach: present your strategy for addressing the problem; describe important findings from your research to date; state the role of this research in advancing knowledge and the state-of-the-art.
  • Objective and Results: what do you plan to accomplish in a 3-year program; what is anticipated output of a successful effort?
  • Funding Request Amount: plan for 3-year program funded by a research contract.
  • Funding Leverage Amount: leverage funds applicable to the proposed research.
  • IP: identify any preexisting intellectual property

Awardees will be expected to:

  • Disclose blocking background intellectual property
  • Update information about participating students
  • Submit publications resulting from sponsored research
  • Participate in annual research reviews
  • Provide annual reports and pre-defined deliverables

Timetable and Deadlines

Event Deadline
Request for White Papers Friday, May 2, 2008
Deadline to Submit White Papers Monday, June 16, 2008 (3:00 p.m. Eastern)
Proposals Requested Thursday, July 31, 2008
Deadline to Submit Proposals Monday, September 15, 2008 (3:00 p.m. Eastern)
Program/Funding Start Thursday, January 1, 2009

Please direct all technical questions to Kwok Ng (
All other questions and responses should be directed to Jacqui Hall (

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