Floating Gate Transistor Having Buried Strained Silicon Germanium Channel Layer

    • Application Type:
      Utility
      Patent Number:
      6313486
      Country:
      United States
      Status:
      Filed on 15-Jun-2000, Issued on 6-Nov-2001
      Organization:
      University of Texas at Austin
      SRC Filing ID:
      P0092

    Inventors

    • David L. Kencke (UT/Austin)
    • Sanjay K. Banerjee (UT/Austin)

    Related Patents

    P0215
    Abandoned Application
    GRC

    Floating Gate Transistor Having Buried Strained Silicon Germanium Channel Layer

    Sanjay K. Banerjee (UT/Austin); David L. Kencke (UT/Austin)
    Patent Application Abandoned
    Application Type: Patent Cooperation Treaty

    INFORMATION

    FOR MEMBERS

    SRC VALUE

    ACADEMIA

    4819 Emperor Blvd, Suite 300 Durham, NC 27703 Voice: (919) 941-9400 Fax: (919) 941-9450

    © 2024 by Semiconductor Research Corporation ®
    Access to information on this website may be limited to member companies,
    participating agencies, and qualified researchers.

    Important Information for the SRC website. This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies. If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. By disabling cookies, some features of the site will not work.