Evaluation of Tunnel FET-based Flip-Flop Designs for Low Power, High Performance Applications

  • Authors:
    Matthew Cotter (Penn State), Huichu Liu (Penn State), Suman Datta (Penn State), Vijaykrishnan Narayanan (Penn State)
    Publication ID:
    P066401
    Publication Type:
    Paper
    Received Date:
    20-Apr-2013
    Last Edit Date:
    21-May-2013
    Research:
    1806.005 (University of Notre Dame)

Abstract

As proliferation of embedded systems and mobile devices increases, power has become one of the most paramount concerns in current microprocessor designs. Technology scaling has provided many benefits in terms of dynamic power; however, static power has become the bottleneck to reducing power. The researchers address this by evaluating Tunnel FETs (TFETs) for use in low-power, high-performance flip-flop designs. Due to the nature of TFETs, several of the flip-flop designs that are evaluated, require additional modifications beyond simple device replacement—most notably the pseudo-static D flip-flop (DFF). The researchers find that despite these additional transistors, the low voltage TFET DFF provides clear advantages in power and energy combined with performance comparable to higher voltage MOSFET and FinFET designs.

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