Circuit, Layout and Performance of ME-MTJ Logic

  • Authors:
    Jonathan Bird (Univ. at Buffalo), Andrew Marshall (UT/Dallas), Nishtha Sharma (UT/Dallas), Peter Dowben (U Nebraska/Lincoln)
    Publication ID:
    P073457
    Publication Type:
    Poster
    Received Date:
    5-Mar-2015
    Last Edit Date:
    6-Aug-2015
    Research:
    2398.001 (University of Nebraska/Lincoln)

Abstract

Here we describe how the magneto-electric magnetic tunnel junction (ME-MTJ) may be implemented to realize a compact set of logic gates, providing significant area savings over CMOS. The two key elements of this scheme are a majority-logic gate, in which a single ME-MTJ is regulated by three separate inputs, and an exclusive-OR gate that can also be realized from a single ME-MTJ. The structure of the majority gate and consists of three separate gate electrodes that are formed on top of the magneto-electric (ME). The other device that may be implemented with the ME-MTJ is an XOR gate. This should be possible by making a simple modification to the MTJ geometry, in which the fixed ferromagnetic layer at the bottom of the stack is replaced by a ferromagnetic layer in contact with an additional ME layer.

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