The Case for Database Processing Units

  • Authors:
    Andrea Lottarini (Columbia), Martha Kim (Columbia), Stephen A. Edwards (Columbia), Kenneth Ross (Columbia)
    Publication ID:
    P084573
    Publication Type:
    Paper
    Received Date:
    24-Jun-2015
    Last Edit Date:
    24-Jun-2015
    Research:
    2384.001 (Harvard University)

Abstract

The increasing capacity and decreasing cost of DRAM has enabled in-memory databases (IMDBs)–database management systems (DBMSs) that rely primarily on main memory for data storage. Simultaneous to the rise of IMDBs, single core processor performance hit the so-called power wall. To keep power dissipation at bay as technology shrinks, large portions of a chip will have to be powered down at any time.

In this context, proposals to accelerate database operations have flourished. However, the integration of these accelerators in a DBMS pose a major challenges. Accelerators require a full materialization of input and output data, which is known to be inefficient. We show how a spatial architecture that connects accelerators using a Network on Chip (NoC) can overcome these difficulties. Our results show an average reduction of memory requests by 49% and a 41% average reduction of query completion time compared to a system with disjoint accelerators.

Past Events

  Event Summary
20–22 September 2015
SRC
SRC
TECHCON 2015
Sunday, Sept. 20, 2015, 8 a.m. — Tuesday, Sept. 22, 2015, 10 p.m. CT
Austin, TX, United States
Technical conference and networking event for SRC members and students.

4819 Emperor Blvd, Suite 300 Durham, NC 27703 Voice: (919) 941-9400 Fax: (919) 941-9450

Important Information for the SRC website. This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies. If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. By disabling cookies, some features of the site will not work.