Hetero-integrated III-V 3D CMOS on InAs/GaSb

  • Authors:
    Heng Wu (Purdue)
    Publication ID:
    P085255
    Publication Type:
    Presentation
    Received Date:
    30-Aug-2015
    Last Edit Date:
    22-Sep-2015
    Research:
    2288.001 (Purdue University)

Abstract

This paper presents a study on III-V 3D nanoscale CMOS on the lattice-matched InAs/GaSb system. Process development was firstly conducted to realize the hetero-integration of InAs nanowire and GaSb fin on the same substrate through a selective wet etching method. Based on this, InAs gate all around (GAA) nanowire MOSFETs are demonstrated by a top-down approach for the first time, showing good ON-and OFF-state performance. Furthermore, interface passivation technique for GaSb is studied and preliminary results on GaSb p-FinFETs are obtained.

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