Hetero-integrated III-V 3D CMOS on InAs/GaSb
This paper presents a study on III-V 3D nanoscale CMOS on the lattice-matched InAs/GaSb system. Process development was firstly conducted to realize the hetero-integration of InAs nanowire and GaSb fin on the same substrate through a selective wet etching method. Based on this, InAs gate all around (GAA) nanowire MOSFETs are demonstrated by a top-down approach for the first time, showing good ON-and OFF-state performance. Furthermore, interface passivation technique for GaSb is studied and preliminary results on GaSb p-FinFETs are obtained.
Sunday, Sept. 20, 2015, 8 a.m. — Tuesday, Sept. 22, 2015, 10 p.m. CT
Austin, TX, United States
Technical conference and networking event for SRC members and students.