Ge Based Nanoscale CMOS Devices and Circuits
This work presents new approaches investigated for future's post-Si technology based on Germanium by both experiments and TCAD simulations. A novel recessed S/D technique is introduced in the MOSFETs fabrication, greatly improving the n-Ge contacts. Low Rc of 0.05 and 0.23 Ω·mm are obtained for p- and n- contacts. For the first time, Ge nMOSFETs is scaled to sub-100 nm node down to 25 nm, with 4X record high Imax and gmax. The world's first CMOS circuits on Ge are demonstrated here through a novel recessed S/D and channel process. First sub-100 nm channel length and record high voltage gain of 36 V/V on non-Silicon substrate are achieved. Logic gates such as inverters, NANDs, NORs and ring oscillators are realized. Advanced gate structures such as ET-SOI, tri-gate and nanowire are further explored, showing much enhanced short channel effect immunity. First 3D FinFETand nanowire CMOScircuit on Ge are also demonstrated.
Sunday, Sept. 20, 2015, 8 a.m. — Tuesday, Sept. 22, 2015, 10 p.m. CT
Austin, TX, United States
Technical conference and networking event for SRC members and students.