A High-Efficiency High-Frequency GaN-Based Three-Level Isolated DC-DC Converter with Dynamic Dead-Time Controlled Synchronous Gate Driver

  • Authors:
    Jing Xue (UT/Dallas), Hoi Lee (UT/Dallas)
    Publication ID:
    P085334
    Publication Type:
    Presentation
    Received Date:
    3-Sep-2015
    Last Edit Date:
    21-Sep-2015
    Research:
    1836.144 (University of Texas/Dallas)

Abstract

This paper presents techniques for high-voltage converters to achieve high power efficiency at high switching frequency. A quasi-square-wave zero-voltage switching isolated three-level half-bridge architecture is proposed to minimize the converter switching loss under high-voltage high-frequency conditions. A synchronous three-level gate driver with dynamic dead-time control is also developed to ensure reliability of all eGaN power FETs, automatically generate appropriate dead-time for all power FETs to achieve ZVS with minimal reverse bias behavior, and provide fast propagation delays for high-frequency converter operation. Implemented in a 0.5-μm HV CMOS process, the proposed gate driver achieves 15ns propagation delays and enables a 100V 35W isolated three-level half-bridge converter to achieve the peak power efficiencies of 95.2% and 90.7% at 1MHz and 2MHz, respectively.

Past Events

  Event Summary
20–22 September 2015
SRC
SRC
TECHCON 2015
Sunday, Sept. 20, 2015, 8 a.m. — Tuesday, Sept. 22, 2015, 10 p.m. CT
Austin, TX, United States
Technical conference and networking event for SRC members and students.

4819 Emperor Blvd, Suite 300 Durham, NC 27703 Voice: (919) 941-9400 Fax: (919) 941-9450