Double Bilayer Graphene Negative Differential Resistance Vertical Interlayer Tunnel FET
The operation of a vertical interlayer tunnel FET using a stacked double bilayer graphene (BLG) and hexagonal boron nitride (hBN) heterostructure is presented. The device is fabricated with a layer-by-layer dry transfer method with the edges of the top and bottom BLG flakes being rotationally aligned to ensure the alignment of the K-point corners of the Brillouin zone of the two graphene layers. The device shows multiple negative differential resistance (NDR) peaks in the interlayer current-voltage characteristic at room temperature which is adjustable through the bottom gate bias. Electrostatic calculations show that the NDR peaks occur when the two sub-bands at the K-point of the top and bottom BLG become aligned at certain bias conditions. Weak temperature dependence was indicative of resonant tunneling. Utilizing the NDR characteristic of the device, a one-transistor latch or SRAM operation is demonstrated.
Sunday, Sept. 20, 2015, 8 a.m. — Tuesday, Sept. 22, 2015, 10 p.m. CT
Austin, TX, United States
Technical conference and networking event for SRC members and students.