Double Bilayer Graphene Negative Differential Resistance Vertical Interlayer Tunnel FET

  • Authors:
    Sangwoo Kang (UT/Austin), Babak Fallahazad (UT/Austin), Kayoung Lee (UT/Austin), Hema Chandra Prakash Movva (UT/Austin), Kyounghwan Kim (UT/Austin), Chris M. Corbet (UT/Austin), Luigi Colombo (TI), Leonard F. Register (UT/Austin), Emanuel Tutuc (UT/Austin), Sanjay K. Banerjee (UT/Austin), Takashi Taniguchi (National Institute for Materials Science), Kenji Watanabe (National Institute for Materials Science3)
    Publication ID:
    Publication Type:
    Received Date:
    Last Edit Date:
    2400.001 (University of Texas/Austin)


The operation of a vertical interlayer tunnel FET using a stacked double bilayer graphene (BLG) and hexagonal boron nitride (hBN) heterostructure is presented. The device is fabricated with a layer-by-layer dry transfer method with the edges of the top and bottom BLG flakes being rotationally aligned to ensure the alignment of the K-point corners of the Brillouin zone of the two graphene layers. The device shows multiple negative differential resistance (NDR) peaks in the interlayer current-voltage characteristic at room temperature which is adjustable through the bottom gate bias. Electrostatic calculations show that the NDR peaks occur when the two sub-bands at the K-point of the top and bottom BLG become aligned at certain bias conditions. Weak temperature dependence was indicative of resonant tunneling. Utilizing the NDR characteristic of the device, a one-transistor latch or SRAM operation is demonstrated.

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20–22 September 2015
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