Auto-Identification and Break of Positive Feedback Loops in Trojan States Vulnerable Circuits
This work introduce a systematic and efficient approach for automatically identifying and breaking all the positive feedback loops in Trojan States Vulnerable Circuit. It first converts the netlist of a circuit into a graphical representation which is called directed dependency graph (DDG). The DDG is subsequently partitioned into strongly connected components (SCCs). For each SCC, existing graph theory techniques are used to detect all PFLs and to determine a minimal break-point set, that is, minimum number of vertices in the graphical representation of the circuit whose removal will break all PFLs. By breaking the PFLs at the circuit nodes corresponding to the elements in the break-point set, break-loop Homotopy methods can be used to generate a multi-dimensional return map from which the presence or absence of Trojan states can be determined. The proposed method greatly enhances the efficiency of loop identification and Trojan State detection especially for large-scale circuits. It was implemented in Cadence Virtuoso as an EDA tool which can automatically highlight and break the loops in circuit schematic.
Sunday, Sept. 20, 2015, 8 a.m. — Tuesday, Sept. 22, 2015, 10 p.m. CT
Austin, TX, United States
Technical conference and networking event for SRC members and students.