A 10Gb/s Hybrid ADC-Based Receiver with Embedded 3-Tap Analog FFE and Dynamically-Enabled Digital Equalization in 65nm CMOS
The use of high speed ADC front-ends in serial link receivers allow for the efficient implementation of powerful equalizers in the digital domain, which enables operation over high attenuation channels. However, the power dissipation of these ADC front-ends, as well as the subsequent digital equalization, is still prohibitive for many systems, where power consumption is a major concern. Novel techniques to reduce complexity and save power, both in the ADC and the digital equalizer are required. In this work, a hybrid ADC-based receiver architecture employs 3-tap analog FFE embedded inside a 6-bit asynchronous SAR ADC and a per-symbol dynamically-enabled digital equalizer to reduce digital equalizer complexity and power consumption. Fabricated in GP 65nm CMOS, the 10Gb/s receiver compensates for up to 36.4dB channel attenuation. Dynamically-enabling the digital 4-tap FFE and 3-tap DFE on a per-symbol basis results in 30mW savings, and an overall receiver power less than 90mW.
Sunday, Sept. 20, 2015, 8 a.m. — Tuesday, Sept. 22, 2015, 10 p.m. CT
Austin, TX, United States
Technical conference and networking event for SRC members and students.