Monolithic 3D Integration of Logic and Memory: Carbon Nanotube FETs, Resistive RAM, and Silicon FETs

  • Authors:
    Max Shulaker (Stanford), Tony Wu (Stanford), Ashish Pal (Stanford), Liang Zhao (Stanford), Yoshio Nishi (Stanford), Krishna C. Saraswat (Stanford), H.-S. Philip Wong (Stanford), Subhasish Mitra (Stanford)
    Publication ID:
    Publication Type:
    Received Date:
    Last Edit Date:
    2385.003 (University of California/Berkeley)


Three-dimensional (3D) integration is an exciting technological option for improving the performance, energy efficiency, and area of gigascale ICs. 3D integration today is typically achieved through chip-stacking, in which multiple vertical circuit layers are connected with ThroughSilicon Vias (TSVs). Rather, monolithic 3D integration, whereby each circuit layer is fabricated directly over the previous circuit layers on the same substrate, uses conventional minimum-sized inter-layer vias (ILVs) to connect multiple circuit layers. The use of conventional vias rather than TSVs allows for increased vertical interconnect density, potentially maximizing the benefits of 3D ICs. Additionally, monolithic 3D integration of logic and memory can further improve performance and energy efficiency benefits, potentially alleviating the logic-memory communication bottleneck. We demonstrate monolithic 3D integration of logic and memory in arbitrary stacking order, with the ability to connect arbitrary circuit layers. This is enabled by integrating traditional silicon-FETs with low processing temperature emerging nanotechnologies: resistive random-access memory (RRAM), and carbon nanotube-FETs (CNFETs). We experimentally show 4 vertically-interleaving layers of logic and memory (a logic layer followed by two memory layers followed by a logic layer); as a demonstration, we fabricate a routing element of a switchbox for an FPGA, with each logic and memory element on a separate layer.

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20–22 September 2015
Sunday, Sept. 20, 2015, 8 a.m. — Tuesday, Sept. 22, 2015, 10 p.m. CT
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