Auto-Identification and Break of Positive Feedback Loops in Trojan States Vulnerable Circuits
A systematic approach is proposed for automatically identifying and breaking positive feedback loops (PFLs) in Trojan States Vulnerable Circuit. The method first converts the netlist of a circuit into a directed dependency graph (DDG) and then partitions the DDG into strongly connected components (SCCs). It then employs graph theory techniques to detect all PFLs and locate the break-points for every SCC. Homotopy methods can then be applied at the break-points to generate a return map from which the presence or absence of Trojan states can be determined. The proposed method greatly enhances the efficiency of loop identification and Trojan State detection especially for large-scale circuits. It was implemented in Cadence Virtuoso as an EDA tool which can automatically highlight and break the loops in circuit schematic. Simulation results using the tool show that the proposed approach can effectively and efficiently identify all the PFLs and break-points of a circuit.
Sunday, Sept. 20, 2015, 8 a.m. — Tuesday, Sept. 22, 2015, 10 p.m. CT
Austin, TX, United States
Technical conference and networking event for SRC members and students.