Report on Initial Fault Injection Experiments
Research Report Highlight
A new hierarchical fault injection simulation framework from UT Austin for modeling single-event upsets can achieve SPICE-level accuracy and 10x faster performance than a baseline RTL simulator, with FPGA acceleration promising another 1000x improvement.
In this work, we present and evaluate a hierarchical fault injection simulation framework for modeling single-event upsets. Combining the circuit, RTL, and ISA levels, and using advanced techniques to eliminate or shorten simulations, the proposed framework can achieve SPICE-level accuracy and, when running in software, 10x faster performance than a baseline RTL simulator. With on-going work in FPGA acceleration, the speedup is expected to increase another three orders of magnitude. The high accuracy and performance attained by the proposed simulation framework would greatly expand the usefulness of fault injection simulations, allowing designers to much more quickly evaluate entire systems’ reliability, with fault tracking capability from circuit nets to application outputs.