A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-based Integral Control in 65nm CMOS
Modern multi-core processors employ multiple phase locked loops (PLLs) to operate individual cores at a power-optimal frequency. This paper presents techniques to implement such PLLs in a small area. The area occupied by classical charge-pump based analog PLLs is mostly due to the large loop filter capacitor needed to implement the integral control portion of type-II response. Digital PLLs (DPLL) can eliminate the capacitor by implementing the integral control in digital domain but their jitter performance is degraded by the quantization error introduced by DPLL building blocks such as a time to digital converter. We seek to combine the advantages of analog (no quantization error) and digital (small area) PLLs by implementing the integral control using time-based techniques. To this end, a ring oscillator based integrator (ROI) is used to implement the integral control. ROI integrates its input and generates an output in the form of a pulse-width-modulated (PWM). While the ROI does not introduce quantization error, controlling the voltage controlled oscillator with the PWM signal introduces undesirable spurious tones. We propose to use a pseudo-differential ROI to mitigate these tones and achieve good jitter performance. Fabricated in 65 nm CMOS LP process, the prototype PLL occupies an active area of only 0.0021mm2, and operates across a supply voltage range of 0.6V to 1.2V providing 0.4-to-2.6 GHz output frequencies. At 2.2 GHz output frequency, the PLL consumes 1.82mW at 1V supply voltage, and achieves 3.73 psrms integrated jitter. This translates to an FoMJ of -226.0 dB, which compares favorably with state-of-art designs while occupying smallest reported active area.