In-memory Computation of a Machine-learning Classifier in a Standard 6T SRAM Array

  • Authors:
    Naveen Verma (Princeton), Zhuo Wang (Princeton), Jintao Zhang (Princeton)
    Publication ID:
    P088593
    Publication Type:
    Paper
    Received Date:
    10-Aug-2016
    Last Edit Date:
    11-Aug-2016
    Research:
    2385.002 (Stanford University)

Abstract

This paper presents a machine-learning classifier where computations are performed in a standard 6T SRAM array, which stores the machine-learning model. Peripheral circuits implement mixed-signal weak classifiers via columns of the SRAM, and a training algorithm enables a strong classifier through boosting and also overcomes circuit nonidealities, by combining multiple columns. A prototype 128×128 SRAM array, implemented in a 130nm CMOS process, demonstrates 10-way classification of MNIST images (using image-pixel features downsampled from 28×28=784 to 9×9=81, which yields baseline accuracy of 90%). In SRAM mode (bit-cell read/write), the prototype operates up to 300 MHz, and in classify mode it operates at 50 MHz, generating a classification every cycle. With accuracy equivalent to a discrete SRAM/digital-MAC system, the system achieves 10-way classification at an energy of 630 pJ per decision, 113× lower than a discrete system with standard training algorithm and 13× lower than a discrete system with proposed training algorithm.