Noise, Aging, and Variation Aware Design using a System-to-Circuit Approach

  • Authors:
    Mehdi Tahoori (KIT)
    Publication ID:
    P089913
    Publication Type:
    e-Workshop
    Received Date:
    7-Dec-2016
    Last Edit Date:
    7-Dec-2016
    Research:
    2448.001 (Karlsruhe Institute of Technology)
    Replay:
    Replay is not available

Abstract

As the minimum feature size continues to shrink, a host of vulnerabilities influence the resiliency of VLSI circuits, such as increased process variation as well as workload-dependent runtime variations due to voltage and thermal fluctuations together with various device and interconnect aging effects. Current approaches for resilient circuit design consider only a small subset of these factors and typically address each of them in isolation. As a result, an over-pessimistic additive design margin, resulting from these sources, is eroding gains from technology scaling. This presentation discusses a holistic cross-layer timing and reliability analysis framework in order to determine more realistic design margins, which is then utilized in the proposed resilient circuit design methodology. We also look into design challenges imposed by energy-constrained systems and provide circuit design and optimization solutions to address those issues.

Past Events

  Event Summary
7 December 2016
GRC
GRC
Noise, Aging, and Variation Aware Resilient System Design using a System‐to‐Circuit Approach
Wednesday, Dec. 7, 2016, 2 p.m.–3 p.m. ET
Durham, NC, United States

E-Workshop

4819 Emperor Blvd, Suite 300 Durham, NC 27703 Voice: (919) 941-9400 Fax: (919) 941-9450

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