Noise, Aging, and Variation Aware Design using a System-to-Circuit Approach
As the minimum feature size continues to shrink, a host of vulnerabilities influence the resiliency of VLSI circuits, such as increased process variation as well as workload-dependent runtime variations due to voltage and thermal fluctuations together with various device and interconnect aging effects. Current approaches for resilient circuit design consider only a small subset of these factors and typically address each of them in isolation. As a result, an over-pessimistic additive design margin, resulting from these sources, is eroding gains from technology scaling. This presentation discusses a holistic cross-layer timing and reliability analysis framework in order to determine more realistic design margins, which is then utilized in the proposed resilient circuit design methodology. We also look into design challenges imposed by energy-constrained systems and provide circuit design and optimization solutions to address those issues.
|Noise, Aging, and Variation Aware Resilient System Design using a System‐to‐Circuit Approach|
Wednesday, Dec. 7, 2016, 2 p.m.–3 p.m. ET
Durham, NC, United States