Ultra-low Power, Secure IoT Platform for Predicting Cardiovascular Diseases

  • Authors:
    Ozgur Sinanoglu (NYU Abu Dhabi), Muhammad Yasin (NYU Abu Dhabi), Temesghen Tekeste Habte (Khalifa University), Hani Saleh (Khalifa University), Baker Mohammad (Khalifa University), Mohammed Ismail (Khalifa University)
    Publication ID:
    P090043
    Publication Type:
    Deliverable Report
    Received Date:
    5-Jan-2017
    Last Edit Date:
    9-Jan-2017
    Research:
    2440.013 (New York University Abu Dhabi)

Abstract

While the plan was to finish the tapeout of a (KU's) biomedical chip with NYU's security features embedded by now, the tapeout was delayed; the tapeout efforts are ongoing these days. The two research teams from KU and NYU have made significant progress however. We have now defined a systematic approach to integrate NYU's security features into any given chip design, with KU's VA processor used as a case study. The attached report describes this approach in great detail and shows implementation and security results. The report has been submitted to a IEEE journal special issue very recently. We have not received any feedback yet.

Here is a brief description:
In this paper, we develop an ultra-low power and secure IoT sensing/preprocessing platform for prediction of ventricular arrhythmia using ECG signals. Our proposed solution is able to predict the on-set of the critical cardiovascular events upto three hours in advance with 86% accuracy. Moreover, the proposed architecture is implemented using an ASIC design flow in 65nm LPE technology; the power it consumes is 62.2% less than that of the state-of-the-art approaches, while occupying 16.0% smaller area. The proposed processor makes use of ECG signals to extract a chip-specific ECG key that enables protection of communication channel. By integrating the ECG key with an existing design-for-trust solution, the proposed platform offers protection also at the hardware level, thwarting hardware security threats such as reverse engineering and counterfeiting. Through efficient sharing of on-chip resources, the overhead of the multi-layered security infrastructure is kept at 9:5% for area and 0:7% for power with no impact on the speed of the design.

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