2D Electrostrictive FETs for Ultra Low Power Circuits and Architectures
This talk will discuss the 2D Electrostrictive Field Effect Transistor (2D-EFET), a steep slope device capable of low power and high performance for post-CMOS computing. Internal voltage amplification, and therefore a sub-60mV/dec subthreshold swing, occurs via a voltage induced strain transduction mechanism. During the application of a gate voltage, an electrostrictive material is actuated, compressing and modulating the channel bandgap. In the OFF state, the device operates with a large bandgap in the OFF state and a reduced bandgap in the ON state. This device is scalable beyond the 10nm node due to its 2D ultrathin body nature and electrostatic integrity and theoretically should operate at higher ON currents compared to state of the art FETs. The talk will cover the operating principals and predicted device characteristics of different 2D-EFET structures. Material choice considerations along with current and future experimental work will be presented.
|Steep Slope Two Dimensional Electrostrictive Field Effect Transistor (2D-EFET)|
Tuesday, Feb. 21, 2017, 4 p.m.–5:30 p.m. ET
Durham, NC, United States