Enabling Chip-to-substrate all-Cu Interconnections: Design of Engineered Bonding Interfaces for Improved Manufacturability and Low-temperature Bonding

  • Authors:
    Kashyap Mohan (Georgia Tech), Ninad Shahane (Georgia Tech), Gustavo Ramos (Atotech), Arnd Kilian (Atotech), Robin Taylor (Atotech), Frank Wei (DISCO Coproration), P. Markondeya Raj (Georgia Tech), Antonia Antoniou (Georgia Tech), Vanessa Smet (Georgia Tech), Rao R. Tummala (Georgia Tech)
    Publication ID:
    P090485
    Publication Type:
    Paper
    Received Date:
    7-Mar-2017
    Last Edit Date:
    8-Mar-2017
    Research:
    2661.002 (Georgia Institute of Technology)

Abstract

This paper presents the design and implementation of engineered nanoscale bonding interfaces as an effective strategy to improve manufacturability of Cu-Cu bonding to the level where it can, for the first time, be applied to chip-to-substrate (C2S) assembly. All-Cu interconnections are highly sought after to meet the escalating electrical, thermal, and reliability requirements of a wide range of emerging digital and analog systems. Such applications require low-cost processes with bonding temperatures and pressures ideally below 200°C and 20MPa, respectively, far from existing solutions established in wafer-level packaging. GT-PRC and its industry partners address this technology gap through innovative designs of bonding interfaces, introducing: 1) novel ultra-thin surface finish metallurgies applied on Cu bumps and pads to prevent oxidation and achieve low-temperature assembly; 2) low-cost fly-cut planarization technique to lower bonding pressures; and 3) low-modulus nanocopper foam caps to provide tolerance to non-coplanarities, and further reduce bonding temperatures and pressures.

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