Enhancing Structural Test with Probabilistic Functional Information
Ensuring high quality integrated circuits can require testing circuits with faults that go beyond traditional fault models, such as stuck-at and transition faults. For example, simple fault models that focus on the inputs and outputs of logic gates may not adequately model defects that occur within standard cells. As a result, the cell-aware fault model was proposed by other researchers to better model and deterministically detect such defects. Unfortunately, the addition of new fault models with more stringent detection conditions can lead to significant increases in the number of patterns that must be applied during test. In this presentation, we will explore approaches to reduce the increase in pattern counts required for cell-aware fault detection. In fact, with appropriate enhancements to the DFT (Design for Testability) circuitry, in some circuits it may even be possible to detect all static cell-aware faults with no additional patterns above those required for 100% stuck-at fault coverage.
|Enhancing Structural Test with Probabilistic Functional Information|
Wednesday, March 8, 2017, 2 p.m.–3 p.m. ET
Durham, NC, United States