Interconnect Design for Evolutionary, and Revolutionary Transistor Technologies

  • Authors:
    Azad J. Naeemi (Georgia Tech), Divya Madapusi Srinivas Prasad (Georgia Tech)
    Publication ID:
    P090659
    Publication Type:
    Paper
    Received Date:
    5-Apr-2017
    Last Edit Date:
    5-Apr-2017
    Research:
    2624.001 (Georgia Institute of Technology)

Abstract

Interconnects are increasingly contributing to the overall delay at advanced technology nodes. It is becoming increasingly important to study the dynamics between the transistor and interconnect parasitics, and optimize interconnect geometries for every device option to enable optimum performance and power. Prior work has shown that interconnect resistance becomes more important than interconnect capacitance in the FinFET technology era. It is shown that with new transistor innovations like FDSOI, and the TFET technology, the implications on the BEOL design paradigm is contrasting to the prior findings with the FinFET technology. For devices like TFET, which are highly resistive, and have low device capacitance, the circuit delay can be improved by sizing interconnects to have lower capacitance, at the cost of higher resistance.

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