Report on the Tape-out and Post-layout Simulation Results of a 1GS/s, 12b Time-interleaved SAR ADC
Research Report Highlight
TxACE researchers at UT/Dallas summarize the tape out and simulation results on a 12b 4-way time-interleaved SAR ADC designed in 65 nm CMOS. Calibration is used for the inter-channel gain, offset, and skew mismatches.
This report summarizes the tape-out and post-layout simulation results of a 4-way time-interleaved SAR ADC array in 65nm CMOS to achieve the 12b, 1GS/s specs. It consists of 4 single channel pipelined SAR ADCs operating at a 250MS/s conversion rate. The design is based on our previous work. The calibration algorithm is implemented in this work to calibrate the inter-channel gain, offset and skew mismatches.