Hardware Demonstration of Stochastic p-bits for Invertible Logic

  • Authors:
    Ahmed Zeeshan Z. Pervaiz (Purdue), Kerem Yunus Camsari (Purdue), Supriyo Datta (Purdue), Lakshmi Anirudh Ghantasala (Purdue)
    Publication ID:
    Publication Type:
    Received Date:
    Last Edit Date:
    2381.004 (University of Minnesota)


The common feature of nearly all logic and memory devices is that they make use of stable units to represent 0’s and 1’s. A completely different paradigm is based on three-terminal stochastic units where the output is a random telegraphic signal that continuously fluctuates between 0 and 1 with a mean that can be tuned. Each such unit could be called a "p-bit" and many such units can be correlated according to a weight matrix that allows each p-bit to receive a weighted contribution from other p-bits in the network. The choice of the weighting matrix allows not only to solve problems of optimization and inference but also to implement precise Boolean functions in an inverted mode. This inverted operation of Boolean gates is particularly striking: Not only do they provide a unique output in response to a set of inputs but also provide all the inputs that are consistent with a given output. The existing demonstrations of accurate invertible logic are intriguing, but they are based on purely software implementations of p-bits and it is natural to ask whether real hardware implementations of these equations would preserve these striking properties.

This paper uses individual micro controllers to emulate p-bits, so that the input and outputs of the p-bits are actual voltages. We present results for a 4-bit ripple carry adder with 48 correlated p-bits and a 4-bit multiplier working in the inverted mode as a factorizer. Our results constitute a first step towards implementing p-bits with nano devices, like stochastic Magnetic Tunnel Junctions.

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