Test Techniques to Approach Several Defects-Per-Billion for Power ICs

  • Authors:
    William R. Eisenstadt (Univ. of Florida)
    Publication ID:
    Publication Type:
    Annual Review
    Received Date:
    Last Edit Date:
    2712.018 (University of Florida)


Task researchers will examine sub-circuit performance inside of LDOs and Buck Converters (example power ICs) in order to achieve several orders of magnitude better discovery of power IC defects. This approach adds additional test points for bare die wafer probe. The test points are either in the wafer scribe lanes that wafer sawing for packaging destroys or are internal IC test pads that packaging makes inaccessible. Bare-die power IC probing allows the measurement of DC and small signal responses of sub-circuits and devices. In addition, bare die probing allows for precise control of wafer temperature and driving wafers to very cold regions of operation (up to -40C).

Past Events

  Event Summary
15–16 May 2017
CAD and Test Review
Monday, May 15, 2017, 1 p.m. — Tuesday, May 16, 2017, 2 p.m. ET
Atlanta, GA, United States

4819 Emperor Blvd, Suite 300 Durham, NC 27703 Voice: (919) 941-9400 Fax: (919) 941-9450

Important Information for the SRC website. This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies. If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. By disabling cookies, some features of the site will not work.