Test Techniques to Approach Several Defects-Per-Billion for Power ICs

  • Authors:
    William R. Eisenstadt (Univ. of Florida)
    Publication ID:
    P090801
    Publication Type:
    Annual Review
    Received Date:
    1-May-2017
    Last Edit Date:
    15-May-2017
    Research:
    2712.018 (University of Florida)

Abstract

Task researchers will examine sub-circuit performance inside of LDOs and Buck Converters (example power ICs) in order to achieve several orders of magnitude better discovery of power IC defects. This approach adds additional test points for bare die wafer probe. The test points are either in the wafer scribe lanes that wafer sawing for packaging destroys or are internal IC test pads that packaging makes inaccessible. Bare-die power IC probing allows the measurement of DC and small signal responses of sub-circuits and devices. In addition, bare die probing allows for precise control of wafer temperature and driving wafers to very cold regions of operation (up to -40C).

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  Event Summary
15–16 May 2017
GRC
GRC
CAD and Test Review
Monday, May 15, 2017, 1 p.m. — Tuesday, May 16, 2017, 2 p.m. ET
Atlanta, GA, United States

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