Accurate ADC Testing with Significantly Relaxed Instrumentation Including Large Cumulative Jitter

  • Authors:
    Li Xu (Iowa St Univ.), Degang Chen (Iowa St Univ.), Yuming Zhuang (Iowa St Univ.), Rajavelu Thinakaran (TI), Kenneth M. Butler (TI)
    Publication ID:
    P090855
    Publication Type:
    Paper
    Received Date:
    8-May-2017
    Last Edit Date:
    8-May-2017
    Research:
    1836.127 (Iowa State University)

Abstract

Spectral testing and linearity testing are two important categories in ADC testing. The sampling clock quality is a crucial factor in ADC spectral testing. The accumulated clock jitter of the sampling clock generates power leakage in the fundamental component of the ADC output spectrum, and the random clock jitter increases the noise floor of the ADC output spectrum, which corrupts the spectrum result of the ADC. This paper proposed a new algorithm to accurately estimate the ADC specifications despite sampling clock jitter. The ADC output sequence is divided into small segments. Each segment is paired with another one, such that their initial phases match with each other the best. By analyzing the difference of each segment pair, the noise power is separated from clock jitter and is estimated accurately. In each segment, by removing the estimated local accumulated jitter, the leakage due to accumulated clock jitter is removed, correct harmonic and non-harmonic spur information is obtained. Simulation and measurement results comparing with the standard test methods corroborated the accuracy and robustness of the new solution. This method significantly relaxed the stringent test requirements on high precision sampling clock and dramatically reduced the test cost and complexity, which offers potential for low cost on-chip testing.

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