Accurate Linearity Testing with Impure Sinusoidal Stimulus Robust Against Flicker Noise
Accurately characterizing linearity performance of high resolution Analog-to-Digital Converters (ADCs) has been a challenging task for many years, as providing input signals whose purity is beyond ADC under test becomes harder and harder as the ADC performance becomes better. This paper proposes a novel method that uses impure test signals to accurately test linearity performance of ADC. Two nonlinear sinusoidal signals with a constant offset in between are applied to the ADC under test to obtain two output data. By identifying nonlinearities from the input and removing these stimulus errors, accurate linearity performance can be obtained. Compared with previous SEIR methods, which is vulnerable to flicker noise inherited in the input signals, the new method uses impure sinusoidal signals instead of ramp signals. Using only -40 to -70dB purity sinusoidal signals, without any Center Symmetric Interleaving (CSI) or Interleaving pattern, the proposed method is much easier to implement, and it can tolerate the influence of flicker noise, while achieving 0.8
least significant bit (LSB) estimation error, which is in the similar level when a pure sinusoidal is used for the same ADC linearity test. The proposed method is analyzed in detail and comparisons are made between previous SEIR methods. The effectiveness and robustness of the proposed method against flicker noise is verified through various simulations. The proposed method helps reduce the production test cost, and simplify the test setup for high resolution ADC linearity test, which is suitable for cost-effective on-chip implementation.