Hierarchical Temporal Memory on the Automata Processor

  • Authors:
    Mateja Putic (Univ. of Virginia), A.J. Varshneya (Univ. of Virginia), Mircea R. Stan (Univ. of Virginia)
    Publication ID:
    P090965
    Publication Type:
    Paper
    Received Date:
    22-May-2017
    Last Edit Date:
    22-May-2017
    Research:
    2384.007 (University of Michigan)

Abstract

Key correspondences between counter-extended nondeterministic finite automata and the hierarchical temporal memory (HTM) activation model indicate use of the automata processor as an efficient hardware accelerator. In this article, the authors introduce a methodology for synthesizing HTM on the automata processor, demonstrate three prediction applications on their model, and show its potential to achieve between 137 to 446 times speedup over the CPU.

4819 Emperor Blvd, Suite 300 Durham, NC 27703 Voice: (919) 941-9400 Fax: (919) 941-9450

Important Information for the SRC website. This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies. If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. By disabling cookies, some features of the site will not work.