Hierarchical Temporal Memory on the Automata Processor

  • Authors:
    Mateja Putic (Univ. of Virginia), A.J. Varshneya (Univ. of Virginia), Mircea R. Stan (Univ. of Virginia)
    Publication ID:
    Publication Type:
    Received Date:
    Last Edit Date:
    2384.007 (University of Michigan)


Key correspondences between counter-extended nondeterministic finite automata and the hierarchical temporal memory (HTM) activation model indicate use of the automata processor as an efficient hardware accelerator. In this article, the authors introduce a methodology for synthesizing HTM on the automata processor, demonstrate three prediction applications on their model, and show its potential to achieve between 137 to 446 times speedup over the CPU.

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