Celerity: An Open Source RISC-V Tiered Accelerator Fabric
Celerity is an SoC architecture developed in 16nm TSMC 16FFC FinFET technology, in nine months from PDK access to tapeout, as part of the DARPA CRAFT program that seeks to develop new methodologies for rapid chip development. The 25 mm2 SoC will be on the April 24th 2017 DARPA TSMC 16nm shuttle and will be back in the lab before the Hotchips conference is held.
Celerity was developed by a team of junior graduate students working across four universities - UCSD, U. Michigan, Cornell, and UCLA. Celerity is 100% open source at the RTL level. The students carried the design end-to-end from RTL to GDS handoff using Synopsys DC and Cadence Innovus. Celerity is possibly the most complex SoC developed to date in academia.