Device-Circuit Analysis of Ferroelectric FETs For Low Power Logic

  • Authors:
    Shreya Gupta (Penn State), Mark Steiner (Penn State), Ahmedullah Aziz (Penn State), Vijaykrishnan Narayanan (Penn State), Suman Datta (Univ. of Notre Dame), Sumeet K. Gupta (Penn State)
    Publication ID:
    P090971
    Publication Type:
    Paper
    Received Date:
    23-May-2017
    Last Edit Date:
    24-May-2017
    Research:
    2657.001 (University of Notre Dame)

Abstract

Ferroelectric FETs (FEFETs) are emerging devices with an immense potential to replace conventional MOSFETs by virtue of their steep switching characteristics. The ferroelectric (FE) material in the gate stack of the FEFET exhibits negative
capacitance resulting in voltage step-up action which entails sub-60mV/decade sub-threshold swing at room temperature. The thickness of the FE layer (TFE) is an important design parameter, governing the device-circuit operation. This paper extensively analyzes the impact of TFE on the device-circuit characteristics in conjunction with the interactions between FE and gate/drain capacitances. While it is well known that increasing TFE yields higher gain albeit with the possibilities of introducing hysteresis, our analysis points to other unconventional effects emerging in circuits as TFE is increased. Depending on the attributes of the underlying transistor, increasing TFE beyond a certain value may lead to loss in saturation and/or negative differential resistance in the output characteristics. While the former effect results in the
loss in gain of a logic gate, the latter may yield hysteretic voltage transfer characteristics. We also discuss the effect of TFE on the circuit energy-delay. Our analysis shows that for high TFE, the delay of the circuit may increase with an increase in supply voltage. However, for voltages < 0.25 V, FEFETs show an immense promise yielding 25% lower energy at iso-delay.

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