Efficient Analog Circuits for Boolean Satisfiability

  • Authors:
    Xunzhao Yin (Univ. of Notre Dame), Behnam Sedighi (Qualcomm), Melinda Varga (Univ. of Notre Dame), Zoltan Toroczkai (Univ. of Notre Dame), Xiaobo Sharon Hu (Univ. of Notre Dame)
    Publication ID:
    P090999
    Publication Type:
    Paper
    Received Date:
    26-May-2017
    Last Edit Date:
    30-May-2017
    Research:
    2698.004 (University of Notre Dame)

Abstract

Efficient solutions to NP-complete problems would significantly benefit both science and industry. However, such problems are intractable on digital computers based on the von Neumann architecture, thus creating the need for alternative solutions to tackle such problems. Recently, a deterministic, continuous-time dynamical system (CTDS) was proposed to solve a representative NP-complete problem, Boolean Satisfiability (SAT). This solver shows polynomial analog time-complexity on even the hardest benchmark k-SAT (k 3) formulas, but at an energy cost through exponentially driven auxiliary variables. With some modifications to the CTDS equations, here we present a novel analog hardware SAT solver, AC-SAT, implementing the CTDS. AC-SAT is intended to be used as a co-processor and is programmable for handling different problem specifications. Furthermore, with its modular design, AC-SAT can be readily extended to solve larger size problems. The circuit is designed and simulated based on a 32nm CMOS technology. SPICE simulation results show speedup factors of ~10(4) on even the hardest 3-SAT problems, when compared with a state-of-the-art SAT solver on digital computers. As an example, for hard problems with N = 50 variables and M = 212 clauses, solutions are found within from a few ns to a few hundred ns with an average power consumption of 130 mW.

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