A New Modular and Globally Optimizing High-level Synthesis Engine for Rapid Post-Silicon Validation of Customized Hardware and Accelerators

  • Authors:
    Subhasish Mitra (Stanford), Deming Chen (UIUC)
    Publication ID:
    P091000
    Publication Type:
    Annual Review
    Received Date:
    26-May-2017
    Last Edit Date:
    6-Jun-2017
    Research:
    2505.001 (University of Illinois/Urbana-Champaign)
    2506.001 (Stanford University)

Abstract

We will present our new research results in four different but related areas: 1) a unified framework for both pre-silicon and post-silicon debug through hybrid QED (Quick Error Detection) methodologies and high-level synthesis; 2) E-QED: electrical bug localization during post-silicon validation enabled by QED and formal methods; 3) Cross-layer resilience study for ASIC accelerators and FPGAs; and 4) New designs for modulo arithmetic functional units for circuit reliability.

Past Events

  Event Summary
31–1 May 2017–June 2017
GRC
GRC
2017 System Level Design Review
Wednesday, May 31, 2017, 8 a.m. — Thursday, June 1, 2017, 5 p.m. ET
Ann Arbor, MI, United States

4819 Emperor Blvd, Suite 300 Durham, NC 27703 Voice: (919) 941-9400 Fax: (919) 941-9450