Report on Latchup Rules for Designs with Reverse Body Bias (RBB)
Research Report Highlight
TxACE researchers at UIUC investigate latchup conditions on circuits that utilize reverse body bias. Measurement results from a testchip are presented and suggested guidelines are given.
This report focuses on latchup that results from the inadvertent triggering of a parasitic PNPN inherent to CMOS logic circuits. One must give special attention to latchup avoidance during the design of a CMOS IC that utilizes Reverse Body Bias (RBB). First, the resistance from the base region of the parasitic PNP [NPN] to the N-well [P-well] bias generator may be large, which will tend to lower the latchup trigger current. Second, system-level ESD may induce differential-mode noise between the N-well bias and VDD, potentially forward-biasing the base-emitter junction of the PNP inside the parasitic PNPN. This report describes a test chip in which the ESD-induced noise between the Nwell bias voltage rail and the supply rail triggered latchup, and it suggests guidelines for reducing latchup hazards in designs with RBB.