Design and Simulation of 3HJ TFETs with Phonon Scattering Effects
VLSI devices are constrained by CVDD2/2 power dissipation. Tunnel FETs (TFETs) have steep subthreshold swings (S.S.) and can operate at low VDD thus low power, yet their ION is limited by low tunneling probability. This low ION results in large CVDD/I delay and slow logic operation. For greatly increased ION, we had proposed a triple-heterojunction (3HJ) TFET design incorporating source and channel heterojunctions (HJ). The designs of have an InAlAsSb channel, yet no low-trap-density dielectric interfaces to InAlAsSb have been reported. In contrast, low-trap-density dielectric interfaces have been demonstrated to InAs, InGaAs, and InP. Here we propose an InGaAs/GaAsSb/InAs/InP 3HJ TFET design, with growth lattice-matched to InP. The gated channel surface is InAs and InP, and thus can have low trap density. The p-type side of the tunnel junction is GaAsSb, instead of strained GaSb, as compressive strain increases the hole transport effective mass reducing the tunneling probability. When simulated assuming incoherent quantum transport, with acoustic and optical phonon scattering modeled, ION remains very high at 516μA/μm.