A 19.4 pJ/Decision 364K Decisions/s In-memory Random Forest Classifier in 6T SRAM Array

  • Authors:
    Mingu Kang (UIUC), Sujan Kumar Gonugondla (UIUC), Naresh Shanbhag (UIUC)
    Publication ID:
    P091081
    Publication Type:
    Paper
    Received Date:
    6-Jun-2017
    Last Edit Date:
    8-Jun-2017
    Research:
    2385.002 (Stanford University)

Abstract

This paper presents IC realization of a random forest (RF) machine learning classifier. Algorithm-architecture circuit is co-optimized to minimize the energy-delay product (EDP). Deterministic subsampling (DSS) and balanced decision trees result in reduced interconnect complexity and avoid irregular memory accesses. Low-swing analog in-memory computations embedded in a standard 6T SRAM enable massively parallel processing thereby minimizing the memory fetches and reducing the EDP further. The 65nm CMOS prototype achieves a 6.8Ă— lower EDP compared to a conventional design at the same accuracy (94%) for an 8-class traffic sign recognition problem.

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