Chip-level ESD-induced Noise on Internally and Externally Regulated Power Supplies

  • Authors:
    Yang Xiu (UIUC), Nicholas Thomson (UIUC), Robert Mertens (NXP), Collin M. Reiman (UIUC), Elyse Rosenbaum (UIUC)
    Publication ID:
    Publication Type:
    Received Date:
    Last Edit Date:
    1836.141 (University of Illinois/Urbana-Champaign)


Power integrity during system-level ESD is studied on two test chips that have different integrated voltage regulator designs. On-chip voltage regulation can provide increased immunity to ESDinduced noise, especially if the internally-generated power supply does not utilize any off-chip decoupling capacitors.

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